The present technique relates to an apparatus and method for controlling use of a register cache.
As data processing systems increase in complexity, the size of the register file (also known as a register bank) accessible to a processor has significantly increased. Modern day processors may implement a variety of different mechanisms aimed at increasing throughput, and may for example allow multiple instructions to be executed simultaneously using different execution pipelines. Register renaming techniques may be used to increase the ability to parallelise instruction execution. This has led to an overall increase in the number or registers provided by the register file, and also has tended to lead to an increase in the number of read and write ports provided for the register file.
As the register file increases in size and complexity, the time taken to access the register file can become significant, and potentially place a timing limitation on the performance of the processor.
One proposal to seek to alleviate the timing constraint resulting from access to the register file is to use a register cache to cache a subset of the data held in the register file. The processor can then attempt to access the required data in the register cache, and only in the event that the data is not in the register cache will an access to the register file be required. In order to improve the benefits available from such an approach, it is desirable to reduce the occurrence of misses within the register cache.